This invention relates generally to direct-digital synthesizers.
As is known in the art, direct-digital synthesizers (DDS) are used extensively for generation of digital sinusoidal signals; both real and complex (quadrature). One capability of DDS is the generation of signals with extremely high frequency resolution. Synthesizers of this type can be used for the generation of precision analog signals when accompanied by a digital to analog converter (DAC). In addition, they can be used as local oscillators for digital up or down-conversion functions. These operations are commonly used in implementations of digital radios and digital modems.
A block diagram of a typical DDS 10 is shown in FIG. 1A for generating sine and/or cosine waveforms. The DDS 10 includes a phase accumulator 12 fed by a phase increment, or frequency control, digital word, X, where (0 less than X less than 2N). The accumulator drives the address input of a read only memory (ROM) 14. The ROM 14 stores digital samples of the sine and/or cosine waveform to be synthesized. The phase output of the accumulator 12 increases linearly with time at a rate proportional to the input frequency control word X and such phase wraps around whenever it exceeds the size of the register 16 in the accumulator 12 loop. The register 16 and a modulo 2N adder 18 in the accumulator 12 loop operate under modulo 2N arithmetic, where N is the wordlength of the phase accumulator governing the frequency resolution of the synthesizer 10 output signal. The phase signal, Y, produced by the accumulator 16 is converted to a sine and/or cosine waveform using the ROM 14 as a look-up table or by using some other means of generating trigonometric functions such as a trigonometric engine, or the CORDIC algorithm. The output frequency, Fout, of the sine and/or cosine waveform generated by the DDS 10 is equal to the rate at which the phase increases per second divided by 2xcfx80, that is
Fout=(X/2N)Fclockxe2x80x83xe2x80x83(1)
where Fclock is the master clock rate fed to the register 16 of the DDS 10. In most applications, not all N bits of the phase output, Y, are used to address the ROM 14 or trigonometric engine. Rather, only the M most significant bits (MSBs) of the phase output, Y, are used to address the ROM 14 and the N-M least significant bits (LSBs) of the phase output Y are truncated. As a consequence of this truncation, phase noise is introduced. In a practical design, the value of M is chosen to meet certain noise and spurious free dynamic range requirements.
The number of output bits L used in the DDS 10 determines the noise due to amplitude quantization and the complexity of any subsequent digital signal processing (DSP) or digital to analog converter (DAC), not shown, used in conjunction (i.e., the output of the ROM 14 is typically followed by a digital to analog converter or DSP. It is generally desirable to keep L and M as low as possible to minimize circuit complexity and power. The noise floor (power spectral density, PSD) due to amplitude quantization may be represented by:
SQ(f)=6.02L+1.8+10log(Fclock/2)dbc/Hzxe2x80x83xe2x80x83(2)
assuming a full scale signal, i.e., X is N bits. Similarly, the spurious free dynamic range (SFDR) due to the phase truncation to M bits may be represented by:
SFDR=6.02Mxe2x88x924(db)xe2x80x83xe2x80x83(3)
The nature of phase truncation is to introduce a periodic error signal made up of a fundamental and several harmonic components. Since this signal is not xe2x80x9cwhitexe2x80x9d, M must be suitably chosen to accommodate the largest spurious tone. Typically, the number of bits M of the phase signal, Y, is larger than the number of bits L of the output of ROM 14 in order to keep the SFDR close to the noise floor dictated by the amplitude quantization.
Another direct-digital synthesizer is described in an article entitled: xe2x80x9cA Direct-Digital Synthesizer with Improved Spectral Performancexe2x80x9d, by Paul O""Leary and Franco Maloberti, published in the IEEE Transactions on Communications, Vol. 39, No. Jul. 7, 1991, pages 1046-1048. Referring to FIG. 4 in such article, here shown in somewhat different form in FIG. 1B, a first-order truncation noise-shaped modulator is in cascade with a conventional phase accumulator. While such system may be useful in some application, the system will not suppress phase noise around the synthesized frequency which suppression is required in other applications. That is, with the system described in the article, the synthesized frequency will contain the sum of phase noise at Tsh(0) and Tsh(2xcfx89o), where Tsh is the phase noise shaped transfer function and xcfx89o is the carrier frequency; however, the phase noise at Tsh(2xcfx89o) is not notched out. Thus, the system is only effective at low frequency xcfx89o where Tsh(2xcfx89o) is still notched out somewhat.
The system described in the above-referenced article was extended to a second-order of noise shaping in an article entitled xe2x80x9cA Direct Digital Synthesizer with a Tunable Feedback Structurexe2x80x9d, by John Vankka, published in the IEEE Transactions on Communications, Vol. 45, No. 4, pages 416-420.
In accordance with the invention, a direct-digital synthesizer is provided for generating a signal having a frequency selected by an input digital word. The synthesizer has a feedback loop to attenuate phase noise of the synthesizer in the neighborhood of the selected frequency of the signal being generated. The synthesizer includes a digital accumulator fed by a phase increment word and responsive to a series clock pulses for successively adding the phase word in response to the clock pulses producing a series of bit phase words. A trigonometric generator is provided for producing sine and cosine digital signals related to the M most significant bits of the phase word. A feedback loop is fed by truncation error words comprising at least a of N-M least significant bits of the N bit phase words producing truncation error words. A complex digital filter is fed by the trigonometric generator for producing real or complex output signals with significantly reduced phase noise artifacts.
In accordance with another embodiment of the invention, a direct-digital synthesizer is provided for generating a waveform. The synthesizer includes a digital accumulator fed by a phase increment word and responsive to a series of clock pulses for successively adding the phase increment word in response to the clock pulses producing a series of N bit phase words. A feedback loop producing N bit truncation error compensated phase words is fed by truncation error words comprising at least a portion of the N-M least significant bits of the truncation error compensated phase words produced therein. A trigonometric generator is provided for producing sine and cosine digital signals related to the M most significant bits of the truncation error compensated phase words. A complex digital filter is fed by the trigonometric generator for producing real or complex output signals with significantly reduced phase noise artifacts.
With such an arrangement, spurious tones are reduced and a lower noise floor is produced. The synthesizer also allows fewer bits of precision to be used to represent the phase output that directly maps to trigonometric values thereby reducing complexity and lowering power.
In accordance with another feature of the invention, the feedback loop includes a digital filter.
In accordance with another feature of the invention, the feedback loop including the digital filter provides a low pass truncation error response to the truncation error having at least one zero in the transfer function thereof at DC.
In accordance with still another feature of the invention, the truncation error response has a transfer function comprising the term (1xe2x88x92azxe2x88x921) where: z is the discrete time frequency variable, and a is a unity or non-unity weighting factor.
In accordance with yet another feature of the invention, the filter includes an adder fed by the truncation error words and a storage device fed by the clock pulses and by the truncation error words for producing at an output thereof the truncation error words delayed by each one of the clock pulses fed thereto. The adder is fed by the output of the storage device to produce an algebraic sum of the truncation error words fed to the adder and the delayed truncation error words produced by the storage device. The output of the adder provides the truncation error compensation words fed to the accumulator along with the phase increment word.
In accordance with still another feature of the invention, a multiplier is included. The multiplier is fed by the truncation error words and by a weighting coefficient to weight the truncation error words by the weighting coefficient prior to feeding such truncation error words to either the adder or the delay device.